Programmable integrated circuits include many individual devices, such as memory cells, on a single circuit chip. The selection of the individual cells for connection to external circuits determines the programming of the integrated circuit. In order to place a particular cell in or out of the overall circuit, a line or link is created between a first or bottom metal layer and a second or top metal layer. The two metal layers can be connected to a source of electrical power for programming purposes. The link acts somewhat on the order of a switch which is either normally open or normally closed. In some pFSB's, these switches can be changed from their normal to their switched position only once and these comprise the write once pFSB's and the like. In addition there are erasable pFSB's such as erasable programmable read only memories (EPROM's) in which the switch may be opened and closed more than once.
When the switchable link is in the form of a normally closed switch, it is known as a "fuse" and, in its original state, the individual memory cell or other device is connected to the outer circuit through the fuse. The fuses are usually made of metal such as an alloy of titanium and tungsten and are relatively easy to fabricate with precision. In programming such a circuit, individual fuses are subjected to a sufficiently high current to destroy or blow the fuse thereby changing the switch from closed to open.
When the switchable link is in the form of a normally open switch, it is known as an "antifuse". The antifuse is formed as a filament of high resistance material which can be converted to a low resistance material. Amorphous silicon is typically used as the antifuse material because it has a high initial resistance but can be converted into a low resistance material merely by the application of a particular voltage. The application of the programming voltage causes the amorphous silicon to melt and crystallize thereby becoming a conductor. In the use of antifuses, there are strict voltage requirements for programming the device and these requirements result in the need for precise thickness of the amorphous silicon used in the antifuse itself. If too low a programming voltage is applied, because the amorphous silicon is too thick, the amorphous silicon is not crystallized. If too high a voltage is applied, it may exceed the maximum tolerated by the related circuitry transistors.
Because reliable fuses are more easily fabricated they are, of course, less expensive. However, fuses are much larger than antifuses and, consequently, antifuses have become more in demand when there is a need for high packing density on a chip.
The amorphous silicon comprising the antifuse is usually located within a via between two levels of the integrated circuit. One of the levels includes a comb like array of conductors in one direction and the other level includes a similar comb like array perpendicular to the first. In the past, these vias have had a diameter of about one micrometer, but design features and compacting of cells on the integrated circuit require smaller and smaller vias.
In early approaches to fabricating the antifuse structure, the antifuse was fabricated on top of an interlevel metal oxide (IMO). The first metal layer was applied on the IMO and acted as its bottom electrode. Amorphous silicon was deposited on the bottom electrode and additional IMO was extended above the amorphous silicon. A via was etched in the silicon dioxide down to the amorphous silicon and the second metal electrode was deposited in the via and in contact with the amorphous silicon. Although it is desirable to fabricate the antifuse consistently with standard ASIC processing, this process was incompatible with the ASIC process since it required the additional metal layer on top of the IMO silicon dioxide and actually required three additional masking steps. Moreover, the etching of the via usually causes some slight change of the amorphous silicon. The via etch should stop at the interface with the amorphous silicon, but usually a few hundred angstroms of amorphous silicon are removed during the etch. Such removal, of course, alters the amorphous silicon's thickness and, as a consequence, the necessary voltage requirements for programming. The variations in the thickness of the amorphous silicon introduce unprogrammed states in the complete device and therefore lead to mortality failures. In order to overcome that problem, an etch stop layer has been deposited on top of the amorphous silicon. The etch stop layer was made thick enough that the via etch did not reach the amorphous silicon lying beneath it, and consequently the programming voltage depended upon the deposition of the amorphous silicon rather than the variability of the etch process. The etch stop could take the form of a conductive layer such as titanium-tungsten (TiW) or it could even be a dielectric such as silicon nitride (SiN).
In one proposed method of fabricating antifuses, amorphous silicon is deposited directly over unetched metal--a sandwich of aluminum-copper between two layers of titanium-tungsten alloy. In the etching of the amorphous silicon layer to define the antifuse structures, there is considerable danger that the etch will be active not only on the amorphous silicon, but also on the underlying metal. There is, therefore, a high risk of etching through the titaniun-tungsten alloy and corroding the underlying aluminum-copper layer. The corrosion may cut completely through the metal layer to make an open circuit. Even if the metal is not sufficiently corroded to create an open circuit, the corrosion is a reliability risk due to electromigration at the corrosion site.
In another recently developed method, a relatively thick layer of silicon dioxide is deposited over the titanium-tungsten strip, and a via is etched through the oxide. The oxide is approximately 300 nm thick and the amorphous silicon is deposited over the planar surface of the oxide and on the oxide walls of the via. However, the amorphous silicon in the via does not deposit in a uniform manner. Rather, furrows are formed in those portions of the amorphous silicon at the base of the vias adjacent the walls thereby creating lines of diminished amorphous silicon thickness. Since the programming voltage is dependent upon the minimum thickness of the amorphous silicon, the furrows create an unacceptable variable. To counter the effect of the furrows, an insulating layer of silicon dioxide is then deposited over the amorphous silicon and the bulk of the oxide is subsequently etched away so as to leave insulating silicon dioxide spacers in the furrows. The spacers effectively prevent the reduced thickness amorphous silicon from being subjected to the programming voltage.